Intel® Stratix® 10 TX 850 FPGA
Specifications
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Essentials
-
Product Collection
Intel® Stratix® 10 TX FPGA
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Marketing Status
Launched
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Launch Date
Q1'18
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Lithography
14 nm
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Resources
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Logic Elements (LE)
841000
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Adaptive Logic Modules (ALM)
284960
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Adaptive Logic Module (ALM) Registers
1139840
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Fabric and I/O Phase-Locked Loops (PLLs)
16
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Maximum Embedded Memory
72 Mb
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Digital Signal Processing (DSP) Blocks
2016
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Digital Signal Processing (DSP) Format
Multiply and Accumulate, Variable Precision, Fixed Point (hard IP), Floating Point (hard IP)
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Hard Processor System (HPS)
Quad-core 64-bit ARM* Cortex*-A53
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, DDR3, DDR2, DDR, QDR II, QDR II+, RLDRAM II, RLDRAM 3, HMC, MoSys
I/O Specifications
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Maximum User I/O Count†
440
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.2 V to 3.3V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL
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Maximum LVDS Pairs
216
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Maximum Non-Return to Zero (NRZ) Transceivers†
72
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Maximum Non-Return to Zero (NRZ) Data Rate†
28.9 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
24
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
57.8 Gbps
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Transceiver Protocol Hard IP
PCIe Gen3, 10/25/100G Ethernet
Advanced Technologies
Package Specifications
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Package Options
F1760, F2397
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Intel® Stratix® 10 TX 850 FPGA 1ST085ES3F50I3XG
- MM# 999FK3
- Spec Code SRFHQ
- Ordering Code 1ST085ES3F50I3XG
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085ES2F50I2LGAS
- MM# 999PJR
- Spec Code SRGZ0
- Ordering Code 1ST085ES2F50I2LGAS
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085EN1F43I1VGBK
- MM# 99A7NK
- Spec Code SRKCF
- Ordering Code 1ST085EN1F43I1VGBK
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085EN2F43I2LGBK
- MM# 99A7NL
- Spec Code SRKCG
- Ordering Code 1ST085EN2F43I2LGBK
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085EN2F43I2VGBK
- MM# 99A7NM
- Spec Code SRKCH
- Ordering Code 1ST085EN2F43I2VGBK
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085EN3F43I3VGBK
- MM# 99A7NN
- Spec Code SRKCJ
- Ordering Code 1ST085EN3F43I3VGBK
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085ES1F50I1VGBK
- MM# 99A7R8
- Spec Code SRKCT
- Ordering Code 1ST085ES1F50I1VGBK
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085ES2F50I2LGBK
- MM# 99A7RN
- Spec Code SRKCU
- Ordering Code 1ST085ES2F50I2LGBK
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085ES2F50I2VGBK
- MM# 99A7T3
- Spec Code SRKCV
- Ordering Code 1ST085ES2F50I2VGBK
- Stepping A1
Intel® Stratix® 10 TX 850 FPGA 1ST085ES3F50I3VGBK
- MM# 99A7TA
- Spec Code SRKCW
- Ordering Code 1ST085ES3F50I3VGBK
- Stepping A1
Trade compliance information
- ECCN 5A002U
- CCATS G178951
- US HTS 8542390001
PCN Information
SRKCT
- 99A7R8 PCN
SRKCU
- 99A7RN PCN
SRKCV
- 99A7T3 PCN
SRKCG
- 99A7NL PCN
SRKCH
- 99A7NM PCN
SRKCJ
- 99A7NN PCN
SRKCF
- 99A7NK PCN
SRFHQ
- 999FK3 PCN
SRFHH
- 999FJP PCN
SRGVU
- 999N43 PCN
SRFHG
- 999FJN PCN
SRGVT
- 999N42 PCN
SRFHF
- 999FJM PCN
SRFHE
- 999FJL PCN
SRFHD
- 999FJK PCN
SRFHC
- 999FJJ PCN
SRFHB
- 999FJC PCN
SRFHA
- 999FJ5 PCN
SRFHP
- 999FK2 PCN
SRFHN
- 999FK1 PCN
SRFHM
- 999FK0 PCN
SRFHL
- 999FJZ PCN
SRFHK
- 999FJX PCN
SRFHJ
- 999FJW PCN
SRGVW
- 999N45 PCN
SRGVV
- 999N44 PCN
SRFGW
- 999FHL PCN
SRFGV
- 999FHK PCN
SRFH7
- 999FJ2 PCN
SRFGU
- 999FHJ PCN
SRFH6
- 999FJ0 PCN
SRFGT
- 999FHH PCN
SRFH5
- 999FHZ PCN
SRFGS
- 999FHG PCN
SRFH4
- 999FHX PCN
SRFH3
- 999FHW PCN
SRFH2
- 999FHV PCN
SRFH1
- 999FHT PCN
SRGVL
- 999N3T PCN
SRFGZ
- 999FHP PCN
SRFGY
- 999FHN PCN
SRFGX
- 999FHM PCN
SRFH9
- 999FJ4 PCN
SRGZ2
- 999PJV PCN
SRFH0
- 999FHR PCN
SRGYZ
- 999PJP PCN
SRGZ1
- 999PJT PCN
SRGZ0
- 999PJR PCN
SRKCW
- 99A7TA PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.