Intel® Stratix® 10 TX 2500 FPGA

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I/O Specifications

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Ordering and Compliance

Ordering and spec information

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU1F50E1VG

  • MM# 986333
  • Spec Code SREXW
  • Ordering Code 1ST250EU1F50E1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU1F50I1VG

  • MM# 986334
  • Spec Code SREXX
  • Ordering Code 1ST250EU1F50I1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50E1VG

  • MM# 986335
  • Spec Code SREXY
  • Ordering Code 1ST250EU2F50E1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50E2LG

  • MM# 986336
  • Spec Code SREXZ
  • Ordering Code 1ST250EU2F50E2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50E2VG

  • MM# 986337
  • Spec Code SREY0
  • Ordering Code 1ST250EU2F50E2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50I1VG

  • MM# 986338
  • Spec Code SREY1
  • Ordering Code 1ST250EU2F50I1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50I2LG

  • MM# 986339
  • Spec Code SREY2
  • Ordering Code 1ST250EU2F50I2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50I2VG

  • MM# 986340
  • Spec Code SREY3
  • Ordering Code 1ST250EU2F50I2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU3F50E3VG

  • MM# 986342
  • Spec Code SREY4
  • Ordering Code 1ST250EU3F50E3VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU3F50E3XG

  • MM# 986343
  • Spec Code SREY5
  • Ordering Code 1ST250EU3F50E3XG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU3F50I3VG

  • MM# 986344
  • Spec Code SREY6
  • Ordering Code 1ST250EU3F50I3VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU3F50I3XG

  • MM# 986346
  • Spec Code SREY7
  • Ordering Code 1ST250EU3F50I3XG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU1F50E2LG

  • MM# 986364
  • Spec Code SREYL
  • Ordering Code 1ST250EU1F50E2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU1F50E2VG

  • MM# 986365
  • Spec Code SREYM
  • Ordering Code 1ST250EU1F50E2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU1F50I2LG

  • MM# 986366
  • Spec Code SREYN
  • Ordering Code 1ST250EU1F50I2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU1F50I2VG

  • MM# 986367
  • Spec Code SREYP
  • Ordering Code 1ST250EU1F50I2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55E1VG

  • MM# 9999CA
  • Spec Code SRF18
  • Ordering Code 1ST250EY1F55E1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55I1VG

  • MM# 9999CC
  • Spec Code SRF19
  • Ordering Code 1ST250EY1F55I1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY2F55E1VG

  • MM# 9999CD
  • Spec Code SRF1A
  • Ordering Code 1ST250EY2F55E1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY2F55E2LG

  • MM# 9999CF
  • Spec Code SRF1B
  • Ordering Code 1ST250EY2F55E2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY2F55E2VG

  • MM# 9999CG
  • Spec Code SRF1C
  • Ordering Code 1ST250EY2F55E2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY2F55I1VG

  • MM# 9999CH
  • Spec Code SRF1D
  • Ordering Code 1ST250EY2F55I1VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY2F55I2LG

  • MM# 9999CJ
  • Spec Code SRF1E
  • Ordering Code 1ST250EY2F55I2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY2F55I2VG

  • MM# 9999CK
  • Spec Code SRF1F
  • Ordering Code 1ST250EY2F55I2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY3F55E3VG

  • MM# 9999CL
  • Spec Code SRF1G
  • Ordering Code 1ST250EY3F55E3VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY3F55E3XG

  • MM# 9999CM
  • Spec Code SRF1H
  • Ordering Code 1ST250EY3F55E3XG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY3F55I3VG

  • MM# 9999CN
  • Spec Code SRF1J
  • Ordering Code 1ST250EY3F55I3VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY3F55I3XG

  • MM# 9999CP
  • Spec Code SRF1K
  • Ordering Code 1ST250EY3F55I3XG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55E2LG

  • MM# 9999D6
  • Spec Code SRF1Y
  • Ordering Code 1ST250EY1F55E2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55E2VG

  • MM# 9999D7
  • Spec Code SRF1Z
  • Ordering Code 1ST250EY1F55E2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55I2LG

  • MM# 9999D8
  • Spec Code SRF20
  • Ordering Code 1ST250EY1F55I2LG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55I2VG

  • MM# 9999D9
  • Spec Code SRF21
  • Ordering Code 1ST250EY1F55I2VG
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50I2VGAS

  • MM# 999G6C
  • Spec Code SRFU3
  • Ordering Code 1ST250EU2F50I2VGAS
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55I2VGAS

  • MM# 999G70
  • Spec Code SRFUL
  • Ordering Code 1ST250EY1F55I2VGAS
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55E2LGAS

  • MM# 99A4G5
  • Spec Code SRK1T
  • Ordering Code 1ST250EY1F55E2LGAS
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU2F50I2VGBK

  • MM# 99A7DG
  • Spec Code SRK8U
  • Ordering Code 1ST250EU2F50I2VGBK
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EY1F55I2VGBK

  • MM# 99A7DP
  • Spec Code SRK90
  • Ordering Code 1ST250EY1F55I2VGBK
  • Stepping C2

Intel® Stratix® 10 TX 2500 FPGA 1ST250EU3F50I3XGAS

  • MM# 99AK9L
  • Spec Code SRKZU
  • Ordering Code 1ST250EU3F50I3XGAS
  • Stepping C2

Trade compliance information

  • ECCN 5A002U
  • CCATS G178951
  • US HTS 8542390001

PCN/MDDS Information

SRF1A

SREY2

SREY1

SRF1H

SREY0

SRF1G

SRF1F

SRF1E

SRF1D

SRF1C

SRF1B

SRK8U

SRF19

SRF18

SRK90

SRF1Z

SRFUL

SREYP

SREYN

SREYM

SREYL

SREXY

SREXX

SRF21

SREXW

SRF20

SRFU3

SREY7

SREY6

SREY5

SREY4

SRF1K

SREY3

SRF1J

SRK1T

SRF1Y

SREXZ

SRKZU

Drivers and Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Processor System (HPS)

The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Maximum Pulse-Amplitude Modulation (PAM4) Transceivers

The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Pulse-Amplitude Modulation (PAM4) Data Rate

The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.