Intel® Stratix® 10 TX 1650 FPGA

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I/O Specifications

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Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU1F50E1VG

  • MM# 986198
  • Spec Code SREVU
  • Ordering Code 1ST165EU1F50E1VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU1F50I1VG

  • MM# 986199
  • Spec Code SREVV
  • Ordering Code 1ST165EU1F50I1VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50E1VG

  • MM# 986200
  • Spec Code SREVW
  • Ordering Code 1ST165EU2F50E1VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50E2LG

  • MM# 986201
  • Spec Code SREVX
  • Ordering Code 1ST165EU2F50E2LG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50E2VG

  • MM# 986202
  • Spec Code SREVY
  • Ordering Code 1ST165EU2F50E2VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50I1VG

  • MM# 986203
  • Spec Code SREVZ
  • Ordering Code 1ST165EU2F50I1VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50I2LG

  • MM# 986204
  • Spec Code SREW0
  • Ordering Code 1ST165EU2F50I2LG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50I2VG

  • MM# 986205
  • Spec Code SREW1
  • Ordering Code 1ST165EU2F50I2VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU3F50E3VG

  • MM# 986206
  • Spec Code SREW2
  • Ordering Code 1ST165EU3F50E3VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU3F50E3XG

  • MM# 986207
  • Spec Code SREW3
  • Ordering Code 1ST165EU3F50E3XG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU3F50I3VG

  • MM# 986208
  • Spec Code SREW4
  • Ordering Code 1ST165EU3F50I3VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU3F50I3XG

  • MM# 986228
  • Spec Code SREW5
  • Ordering Code 1ST165EU3F50I3XG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU1F50E2LG

  • MM# 986243
  • Spec Code SREWJ
  • Ordering Code 1ST165EU1F50E2LG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU1F50E2VG

  • MM# 986244
  • Spec Code SREWK
  • Ordering Code 1ST165EU1F50E2VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU1F50I2LG

  • MM# 986372
  • Spec Code SREYU
  • Ordering Code 1ST165EU1F50I2LG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU1F50I2VG

  • MM# 986373
  • Spec Code SREYV
  • Ordering Code 1ST165EU1F50I2VG
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50I2LGAS

  • MM# 999GJA
  • Spec Code SRFWT
  • Ordering Code 1ST165EU2F50I2LGAS
  • Stepping B0

Intel® Stratix® 10 TX 1650 FPGA 1ST165EU2F50I2VGAS

  • MM# 999GJL
  • Spec Code SRFWU
  • Ordering Code 1ST165EU2F50I2VGAS
  • Stepping B0

Trade compliance information

  • ECCN 3A001.A.7.B
  • CCATS G171972
  • US HTS 8542390001

PCN/MDDS Information

SREW0

SREWK

SREWJ

SREVW

SREVV

SREVU

SRFWU

SREW5

SRFWT

SREW4

SREYV

SREW3

SREYU

SREW2

SREW1

SREVZ

SREVY

SREVX

Drivers and Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Maximum Pulse-Amplitude Modulation (PAM4) Transceivers

The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Pulse-Amplitude Modulation (PAM4) Data Rate

The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

Hyper-Registers

Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.