Intel® MAX® 10 10M40 FPGA
Specifications
Compare Intel® Products
Essentials
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Product Collection
Intel® MAX® 10 FPGA
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Marketing Status
Launched
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Launch Date
2014
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Lithography
55 nm
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Resources
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Logic Elements (LE)
40000
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Fabric and I/O Phase-Locked Loops (PLLs)
4
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Maximum Embedded Memory
1.26 Mb
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Digital Signal Processing (DSP) Format
Multiply
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Hard Memory Controllers
No
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External Memory Interfaces (EMIF)
DDR2 SDRAM, DDR3 SDRAM, LPDDR2, SRAM
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User-Flashable Memory
Yes
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Internal Configuration Storage
Yes
I/O Specifications
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Maximum User I/O Count†
500
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I/O Standards Support
3.0 V to 3.3 V LVTTL, 1.0 V to 3.3 V LVCMOS, PCI, SSTL, HSTL, HSUL, Differential SSTL, Differential HSTL, Differential HSUL, LVDS, Mini-LVDS, RSDS, LVPECL, PPDS, BLVDS, TMDS, Sub-LVDS, SLVS, HiSpi
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Maximum LVDS Pairs
30
Advanced Technologies
Package Specifications
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Package Options
F256, F484, F672, E144
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Trade compliance information
- ECCN Varies By Product
- CCATS NA
- US HTS 8542390001
PCN Information
SR4PN
- 965618 PCN
SR4PM
- 965617 PCN
SR4PL
- 965616 PCN
SR4PK
- 965615 PCN
SR6HK
- 967770 PCN
SR5ZF
- 967145 PCN
SR5ZE
- 967144 PCN
SR5ZD
- 967143 PCN
SRBKH
- 973681 PCN
SR4PJ
- 965614 PCN
SR6T4
- 968113 PCN
SR6T3
- 968112 PCN
SR6T2
- 968111 PCN
SRBKG
- 973680 PCN
SRBKF
- 973679 PCN
SRBKE
- 973678 PCN
SR4P6
- 965600 PCN
SR4P5
- 965599 PCN
SR6T5
- 968114 PCN
SR7DR
- 968826 PCN
SR7DQ
- 968825 PCN
SR7DP
- 968824 PCN
SR4DQ
- 965268 PCN
SR4DP
- 965267 PCN
SRGDK
- 999JFW PCN
Drivers and Software
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Date
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
User-Flashable Memory
User-flashable memory is a non-volatile memory resource available in some Intel FPGA device families.
Internal Configuration Storage
Intel FPGAs store configuration data either in internal configuration storage, or in external memory devices.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Analog-to-Digital Converter
The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.