Intel® MAX® 10 10M02 FPGA

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Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Intel® MAX® 10 10M02 FPGA 10M02DCV36I7G

  • MM# 968811
  • Spec Code SR7DB
  • Ordering Code 10M02DCV36I7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02DCU324A7G

  • MM# 965250
  • Spec Code SR4D7
  • Ordering Code 10M02DCU324A7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02DCU324C8G

  • MM# 968095
  • Spec Code SR6SM
  • Ordering Code 10M02DCU324C8G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCE144A7G

  • MM# 965576
  • Spec Code SR4NH
  • Ordering Code 10M02SCE144A7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02DCV36C8G

  • MM# 973658
  • Spec Code SRBJV
  • Ordering Code 10M02DCV36C8G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCU169I7G

  • MM# 965480
  • Spec Code SR4KR
  • Ordering Code 10M02SCU169I7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCM153C8G

  • MM# 965253
  • Spec Code SR4DA
  • Ordering Code 10M02SCM153C8G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCU169A7G

  • MM# 967746
  • Spec Code SR6GV
  • Ordering Code 10M02SCU169A7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCU169C8G

  • MM# 968096
  • Spec Code SR6SN
  • Ordering Code 10M02SCU169C8G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02DCU324I7G

  • MM# 967745
  • Spec Code SR6GU
  • Ordering Code 10M02DCU324I7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02DCV36C7G

  • MM# 965479
  • Spec Code SR4KQ
  • Ordering Code 10M02DCV36C7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCU324C8G

  • MM# 978978
  • Spec Code SRCYW
  • Ordering Code 10M02SCU324C8G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCE144I7G

  • MM# 965252
  • Spec Code SR4D9
  • Ordering Code 10M02SCE144I7G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCE144C8G

  • MM# 965251
  • Spec Code SR4D8
  • Ordering Code 10M02SCE144C8G
  • Stepping A1

Intel® MAX® 10 10M02 FPGA 10M02SCM153I7G

  • MM# 967126
  • Spec Code SR5Z0
  • Ordering Code 10M02SCM153I7G
  • Stepping A1

Trade compliance information

  • ECCN EAR99
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR7DB

SR4DA

SR6SN

SR6SM

SR4KR

SR4KQ

SR6GV

SR6GU

SRCYW

SR4NH

SRBJV

SR5Z0

SR4D9

SR4D8

SR4D7

Drivers and Software

Latest Drivers & Software

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Name

Technical Documentation

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

User-Flashable Memory

User-flashable memory is a non-volatile memory resource available in some Intel FPGA device families.

Internal Configuration Storage

Intel FPGAs store configuration data either in internal configuration storage, or in external memory devices.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.