MAX® II EPM240 CPLD
Specifications
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Essentials
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Product Collection
MAX® II CPLD
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Marketing Status
Launched
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Launch Date
Q1'14
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Lithography
180 nm
Resources
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Equivalent Macrocells
192
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Pin-to-pin Delay
7.5 ns
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User Flash Memory
8 Kb
Features
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Boundary-scan JTAG
Yes
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JTAG ISP
Yes
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Fast Input Registers
Yes
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Programmable Register Power-up
Yes
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JTAG Translator
Yes
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Real-time ISP
Yes
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MultiVolt I/Os†
1.5, 1.8, 2.5, 3.3
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I/O Power Banks
2
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Maximum Output Enables
80
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LVTTL/LVCMOS
Yes
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Schmitt Triggers
Yes
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Programmable Slew Rate
Yes
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Programmable Pull-up Resistors
Yes
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Programmable GND Pins
Yes
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Open-drain Outputs
Yes
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Bus Hold
Yes
Package Specifications
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Package Options
M100, F100, T100
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Package Size
6mm x 6mm, 11mm x 11mm, 16mm x 16mm
Supplemental Information
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Additional Information
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Ordering and Compliance
Ordering and spec information
Trade compliance information
- ECCN EAR99
- CCATS NA
- US HTS 8542390001
PCN Information
SR6RQ
- 968064 PCN
SRBZV
- 974601 PCN
SRAX4
- 972851 PCN
SRBZU
- 974600 PCN
SR9KN
- 971383 PCN
SR6AF
- 967523 PCN
SRAX1
- 972848 PCN
SR6AD
- 967521 PCN
SR8NM
- 970381 PCN
SR9KR
- 971386 PCN
SR9KQ
- 971385 PCN
SR9TG
- 972156 PCN
SR9TE
- 972154 PCN
SRBAH
- 973377 PCN
Drivers and Software
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Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Equivalent Macrocells
Typical equivalent macrocell" ratio is approximately 1.3 LEs per macrocell based on empirical data.
Pin-to-pin Delay
Pin-to-pin delay is the time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.
User Flash Memory
The User Flash Memory (UFM) provides access to the serial flash memory blocks in these devices.
Boundary-scan JTAG
Testing that isolates a device's internal circuitry from its I/O circuitry.
JTAG ISP
In-System Programmability via JTAG interface.
Fast Input Registers
Input registers in I/O cells that have a fast, direct connection from I/O pins.
Programmable Register Power-up
Enable registered outputs to drive high for a specific duration upon power-up through the Quartus II software.
JTAG Translator
Allow access to the JTAG TAP and state signals when either the USER0 or USER1 instruction is issued to the JTAG TAP.
Real-time ISP
Can program the supported device while the device is still in operation.
MultiVolt I/Os†
Allow devices in all packages to interface with systems of different supply voltages. †An external resistor must be used for 5.0 V tolerance.
I/O Power Banks
A group of I/O pins that are grouped for the purpose of specifying I/O standards. To be powered up during device operation.
Maximum Output Enables
Maximum number of control inputs that either permit or prevent the output of data from the device.
LVTTL/LVCMOS
Low Voltage Transistor to Transistor Logic / Low Voltage Complementary Metal Oxide Semiconductor
Schmitt Triggers
Allow input buffers to respond to slow input edge rates with a fast output edge rate.
Programmable Slew Rate
Output slew rate control that can be configured for low noise or high-speed performance.
Programmable Pull-up Resistors
Each I/O pin on the device provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor holds the output to the VCCIO level of the output pin’s bank.
Programmable GND Pins
Each unused I/O pin on the device can be used as an additional ground pin.
Open-drain Outputs
Devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals that can be asserted by any of several devices.
Bus Hold
Each I/O pin on the device provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
Give Feedback
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.