MAX® II EPM240 CPLD

Specifications

Package Specifications

  • Package Options M100, F100, T100
  • Package Size 6mm x 6mm, 11mm x 11mm, 16mm x 16mm

Supplemental Information

Ordering and Compliance

Ordering and spec information

MAX® II EPM240 CPLD EPM240GT100C3

  • MM# 967521
  • Spec Code SR6AD
  • Ordering Code EPM240GT100C3
  • Stepping A1

MAX® II EPM240 CPLD EPM240T100C4

  • MM# 967523
  • Spec Code SR6AF
  • Ordering Code EPM240T100C4
  • Stepping A1

MAX® II EPM240 CPLD EPM240GM100I5N

  • MM# 968064
  • Spec Code SR6RQ
  • Ordering Code EPM240GM100I5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240T100I5

  • MM# 970381
  • Spec Code SR8NM
  • Ordering Code EPM240T100I5
  • Stepping A1

MAX® II EPM240 CPLD EPM240GT100I5

  • MM# 971383
  • Spec Code SR9KN
  • Ordering Code EPM240GT100I5
  • Stepping A1

MAX® II EPM240 CPLD EPM240T100C5N

  • MM# 971385
  • Spec Code SR9KQ
  • Ordering Code EPM240T100C5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240T100I5N

  • MM# 971386
  • Spec Code SR9KR
  • Ordering Code EPM240T100I5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240GF100I5N

  • MM# 972154
  • Spec Code SR9TE
  • Ordering Code EPM240GF100I5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240M100C5N

  • MM# 972156
  • Spec Code SR9TG
  • Ordering Code EPM240M100C5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240F100C5N

  • MM# 972848
  • Spec Code SRAX1
  • Ordering Code EPM240F100C5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240M100I5N

  • MM# 972851
  • Spec Code SRAX4
  • Ordering Code EPM240M100I5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240GT100C5N

  • MM# 973377
  • Spec Code SRBAH
  • Ordering Code EPM240GT100C5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240GM100C5N

  • MM# 974600
  • Spec Code SRBZU
  • Ordering Code EPM240GM100C5N
  • Stepping A1

MAX® II EPM240 CPLD EPM240T100C3N

  • MM# 974601
  • Spec Code SRBZV
  • Ordering Code EPM240T100C3N
  • Stepping A1

Trade compliance information

  • ECCN EAR99
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR6RQ

SRBZV

SRAX4

SRBZU

SR9KN

SR6AF

SRAX1

SR6AD

SR8NM

SR9KR

SR9KQ

SR9TG

SR9TE

SRBAH

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Equivalent Macrocells

Typical equivalent macrocell" ratio is approximately 1.3 LEs per macrocell based on empirical data.

Pin-to-pin Delay

Pin-to-pin delay is the time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.

User Flash Memory

The User Flash Memory (UFM) provides access to the serial flash memory blocks in these devices.

Boundary-scan JTAG

Testing that isolates a device's internal circuitry from its I/O circuitry.

JTAG ISP

In-System Programmability via JTAG interface.

Fast Input Registers

Input registers in I/O cells that have a fast, direct connection from I/O pins.

Programmable Register Power-up

Enable registered outputs to drive high for a specific duration upon power-up through the Quartus II software.

JTAG Translator

Allow access to the JTAG TAP and state signals when either the USER0 or USER1 instruction is issued to the JTAG TAP.

Real-time ISP

Can program the supported device while the device is still in operation.

MultiVolt I/Os†

Allow devices in all packages to interface with systems of different supply voltages. An external resistor must be used for 5.0 V tolerance.

I/O Power Banks

A group of I/O pins that are grouped for the purpose of specifying I/O standards. To be powered up during device operation.

Maximum Output Enables

Maximum number of control inputs that either permit or prevent the output of data from the device.

LVTTL/LVCMOS

Low Voltage Transistor to Transistor Logic / Low Voltage Complementary Metal Oxide Semiconductor

Schmitt Triggers

Allow input buffers to respond to slow input edge rates with a fast output edge rate.

Programmable Slew Rate

Output slew rate control that can be configured for low noise or high-speed performance.

Programmable Pull-up Resistors

Each I/O pin on the device provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor holds the output to the VCCIO level of the output pin’s bank.

Programmable GND Pins

Each unused I/O pin on the device can be used as an additional ground pin.

Open-drain Outputs

Devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals that can be asserted by any of several devices.

Bus Hold

Each I/O pin on the device provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.