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  • Brand Name: Core i7

  • Product Number: i7-12700KF

  • Ordering Code: CM8071504553829

  • SPEC Code: SRL4P

  • Code Name: Alder Lake

MAX® II EPM1270 CPLD

Specifications

Export specifications

Essentials

Package Specifications

  • Package Options M256, F256, T144
  • Package Size 11mm x 11mm, 17mm x 17mm, 22mm x 22mm

Supplemental Information

Ordering and Compliance

Ordering and spec information

MAX® II EPM1270 CPLD EPM1270F256C5

  • MM# 967512
  • Spec Code SR6A4
  • Ordering Code EPM1270F256C5
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 696292

MAX® II EPM1270 CPLD EPM1270GF256I5

  • MM# 968052
  • Spec Code SR6RC
  • Ordering Code EPM1270GF256I5
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 692214

MAX® II EPM1270 CPLD EPM1270T144A5N

  • MM# 968054
  • Spec Code SR6RE
  • Ordering Code EPM1270T144A5N
  • Stepping A1
  • ECCN EAR99
  • MDDS Content IDs 696531

MAX® II EPM1270 CPLD EPM1270T144C4

  • MM# 968055
  • Spec Code SR6RF
  • Ordering Code EPM1270T144C4
  • Stepping A1
  • ECCN EAR99
  • MDDS Content IDs 702742

MAX® II EPM1270 CPLD EPM1270T144C3

  • MM# 970371
  • Spec Code SR8NB
  • Ordering Code EPM1270T144C3
  • Stepping A1
  • ECCN EAR99
  • MDDS Content IDs 701759

MAX® II EPM1270 CPLD EPM1270GF256C3N

  • MM# 971371
  • Spec Code SR9KA
  • Ordering Code EPM1270GF256C3N
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 694762

MAX® II EPM1270 CPLD EPM1270M256C4N

  • MM# 971374
  • Spec Code SR9KD
  • Ordering Code EPM1270M256C4N
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 696445

MAX® II EPM1270 CPLD EPM1270GT144C4N

  • MM# 972143
  • Spec Code SR9T3
  • Ordering Code EPM1270GT144C4N
  • Stepping A1
  • ECCN EAR99
  • MDDS Content IDs 701742

MAX® II EPM1270 CPLD EPM1270F256C3

  • MM# 972836
  • Spec Code SRAWP
  • Ordering Code EPM1270F256C3
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 694805

MAX® II EPM1270 CPLD EPM1270F256C4N

  • MM# 972838
  • Spec Code SRAWR
  • Ordering Code EPM1270F256C4N
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 691863

MAX® II EPM1270 CPLD EPM1270F256I5

  • MM# 972839
  • Spec Code SRAWS
  • Ordering Code EPM1270F256I5
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 701039

MAX® II EPM1270 CPLD EPM1270GF256I5N

  • MM# 972841
  • Spec Code SRAWU
  • Ordering Code EPM1270GF256I5N
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 691579

MAX® II EPM1270 CPLD EPM1270T144C5

  • MM# 972844
  • Spec Code SRAWX
  • Ordering Code EPM1270T144C5
  • Stepping A1
  • ECCN EAR99
  • MDDS Content IDs 691905

MAX® II EPM1270 CPLD EPM1270T144I5

  • MM# 972846
  • Spec Code SRAWZ
  • Ordering Code EPM1270T144I5
  • Stepping A1
  • ECCN EAR99
  • MDDS Content IDs 697956

MAX® II EPM1270 CPLD EPM1270GF256C4N

  • MM# 973366
  • Spec Code SRBA6
  • Ordering Code EPM1270GF256C4N
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 695601

MAX® II EPM1270 CPLD EPM1270T144C3N

  • MM# 973368
  • Spec Code SRBA8
  • Ordering Code EPM1270T144C3N
  • Stepping A1
  • ECCN EAR99
  • MDDS Content IDs 691787

MAX® II EPM1270 CPLD EPM1270GF256C3

  • MM# 974594
  • Spec Code SRBZN
  • Ordering Code EPM1270GF256C3
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 700039

MAX® II EPM1270 CPLD EPM1270M256C5N

  • MM# 974596
  • Spec Code SRBZQ
  • Ordering Code EPM1270M256C5N
  • Stepping A1
  • ECCN 3A991
  • MDDS Content IDs 697122

Trade compliance information

  • ECCN Varies By Product
  • CCATS NA
  • US HTS 8542390001

PCN Information

SRBZN

SR9KD

SR9KA

SRAWS

SRAWR

SRAWP

SRBA8

SRBZQ

SR9T3

SRBA6

SRAWZ

SRAWX

SRAWU

SR8NB

SR6RF

SR6A4

SR6RE

SR6RC

Drivers and Software

Latest Drivers & Software

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Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Equivalent Macrocells

Typical equivalent macrocell" ratio is approximately 1.3 LEs per macrocell based on empirical data.

Pin-to-pin Delay

Pin-to-pin delay is the time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.

User Flash Memory

The User Flash Memory (UFM) provides access to the serial flash memory blocks in these devices.

Boundary-scan JTAG

Testing that isolates a device's internal circuitry from its I/O circuitry.

JTAG ISP

In-System Programmability via JTAG interface.

Fast Input Registers

Input registers in I/O cells that have a fast, direct connection from I/O pins.

Programmable Register Power-up

Enable registered outputs to drive high for a specific duration upon power-up through the Quartus II software.

JTAG Translator

Allow access to the JTAG TAP and state signals when either the USER0 or USER1 instruction is issued to the JTAG TAP.

Real-time ISP

Can program the supported device while the device is still in operation.

MultiVolt I/Os†

Allow devices in all packages to interface with systems of different supply voltages. †An external resistor must be used for 5.0 V tolerance.

I/O Power Banks

A group of I/O pins that are grouped for the purpose of specifying I/O standards. To be powered up during device operation.

Maximum Output Enables

Maximum number of control inputs that either permit or prevent the output of data from the device.

LVTTL/LVCMOS

Low Voltage Transistor to Transistor Logic / Low Voltage Complementary Metal Oxide Semiconductor

32 bit, 66 MHz PCI Compliant

Note: this product requires an external resistor for 5V tolerance.

Schmitt Triggers

Allow input buffers to respond to slow input edge rates with a fast output edge rate.

Programmable Slew Rate

Output slew rate control that can be configured for low noise or high-speed performance.

Programmable Pull-up Resistors

Each I/O pin on the device provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor holds the output to the VCCIO level of the output pin’s bank.

Programmable GND Pins

Each unused I/O pin on the device can be used as an additional ground pin.

Open-drain Outputs

Devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals that can be asserted by any of several devices.

Bus Hold

Each I/O pin on the device provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.

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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.

Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.

Refer to Datasheet for formal definitions of product properties and features.

‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.

“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.