Ordering and Compliance

Ordering and spec information

MAX® V 5M2210Z CPLD 5M2210ZF256C4N

  • MM# 965739
  • Spec Code SR4T6
  • Ordering Code 5M2210ZF256C4N
  • Stepping A1

MAX® V 5M2210Z CPLD 5M2210ZF324I5N

  • MM# 965740
  • Spec Code SR4T7
  • Ordering Code 5M2210ZF324I5N
  • Stepping A1

MAX® V 5M2210Z CPLD 5M2210ZF256I5N

  • MM# 968261
  • Spec Code SR6XE
  • Ordering Code 5M2210ZF256I5N
  • Stepping A1

MAX® V 5M2210Z CPLD 5M2210ZF256C5N

  • MM# 968401
  • Spec Code SR71D
  • Ordering Code 5M2210ZF256C5N
  • Stepping A1

MAX® V 5M2210Z CPLD 5M2210ZF256I5

  • MM# 968404
  • Spec Code SR71E
  • Ordering Code 5M2210ZF256I5
  • Stepping A1

MAX® V 5M2210Z CPLD 5M2210ZF324C5N

  • MM# 969750
  • Spec Code SR85W
  • Ordering Code 5M2210ZF324C5N
  • Stepping A1

MAX® V 5M2210Z CPLD 5M2210ZF324C4N

  • MM# 970649
  • Spec Code SR8VW
  • Ordering Code 5M2210ZF324C4N
  • Stepping A1

MAX® V 5M2210Z CPLD 5M2210ZF324I5

  • MM# 973791
  • Spec Code SRBNL
  • Ordering Code 5M2210ZF324I5
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • US HTS 8542390001

PCN/MDDS Information









Drivers and Software

Latest Drivers & Software

Downloads Available:


Technical Documentation

Launch Date

The date the product was first introduced.


Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Equivalent Macrocells

Typical equivalent macrocell" ratio is approximately 1.3 LEs per macrocell based on empirical data.

Pin-to-pin Delay

Pin-to-pin delay is the time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.

User Flash Memory

The User Flash Memory (UFM) provides access to the serial flash memory blocks in these devices.

Logic Convertible To Memory

Unused LEs can be converted to memory. The total number of available LE RAM bits depends on the memory mode, depth and width configurations of the instantiated memory.

Internal Oscillator

The internal oscillator is used to meet the clocking requirements of many designs and eliminate the requirement for an external clock circuitry.

Fast Power-on Reset

Fast reset of the entire design to an initial and well-known state after the power supply is detected.

Boundary-scan JTAG

Testing that isolates a device's internal circuitry from its I/O circuitry.


In-System Programmability via JTAG interface.

Fast Input Registers

Input registers in I/O cells that have a fast, direct connection from I/O pins.

Programmable Register Power-up

Enable registered outputs to drive high for a specific duration upon power-up through the Quartus II software.

JTAG Translator

Allow access to the JTAG TAP and state signals when either the USER0 or USER1 instruction is issued to the JTAG TAP.

Real-time ISP

Can program the supported device while the device is still in operation.

MultiVolt I/Os†

Allow devices in all packages to interface with systems of different supply voltages. An external resistor must be used for 5.0 V tolerance.

I/O Power Banks

A group of I/O pins that are grouped for the purpose of specifying I/O standards. To be powered up during device operation.

Maximum Output Enables

Maximum number of control inputs that either permit or prevent the output of data from the device.


Low Voltage Transistor to Transistor Logic / Low Voltage Complementary Metal Oxide Semiconductor

Emulated LVDS Outputs

Low Voltage Differential Signaling outputs

32 bit, 66 MHz PCI Compliant

Note: this product requires an external resistor for 5V tolerance.

Schmitt Triggers

Allow input buffers to respond to slow input edge rates with a fast output edge rate.

Programmable Slew Rate

Output slew rate control that can be configured for low noise or high-speed performance.

Programmable Pull-up Resistors

Each I/O pin on the device provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor holds the output to the VCCIO level of the output pin’s bank.

Programmable GND Pins

Each unused I/O pin on the device can be used as an additional ground pin.

Open-drain Outputs

Devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals that can be asserted by any of several devices.

Bus Hold

Each I/O pin on the device provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.