MAX® II EPM2210 CPLD

MAX® II EPM2210 CPLD

Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

MAX® II EPM2210 CPLD EPM2210GF324I5

  • MM# 967519
  • Spec Code SR6AB
  • Ordering Code EPM2210GF324I5
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F256C4N

  • MM# 968057
  • Spec Code SR6RH
  • Ordering Code EPM2210F256C4N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F324C5N

  • MM# 968060
  • Spec Code SR6RL
  • Ordering Code EPM2210F324C5N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210GF324I5N

  • MM# 968062
  • Spec Code SR6RN
  • Ordering Code EPM2210GF324I5N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F324C3

  • MM# 970373
  • Spec Code SR8ND
  • Ordering Code EPM2210F324C3
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210GF256C5

  • MM# 970376
  • Spec Code SR8NG
  • Ordering Code EPM2210GF256C5
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F324A5N

  • MM# 971377
  • Spec Code SR9KG
  • Ordering Code EPM2210F324A5N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F324C4N

  • MM# 971379
  • Spec Code SR9KJ
  • Ordering Code EPM2210F324C4N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210GF256C4

  • MM# 971380
  • Spec Code SR9KK
  • Ordering Code EPM2210GF256C4
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210GF256C4N

  • MM# 971381
  • Spec Code SR9KL
  • Ordering Code EPM2210GF256C4N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F256A5

  • MM# 972144
  • Spec Code SR9T4
  • Ordering Code EPM2210F256A5
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F256C4

  • MM# 972146
  • Spec Code SR9T6
  • Ordering Code EPM2210F256C4
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F256I5

  • MM# 972148
  • Spec Code SR9T8
  • Ordering Code EPM2210F256I5
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210GF324C5

  • MM# 972152
  • Spec Code SR9TC
  • Ordering Code EPM2210GF324C5
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F324I5

  • MM# 973372
  • Spec Code SRBAC
  • Ordering Code EPM2210F324I5
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210F324I5N

  • MM# 973373
  • Spec Code SRBAD
  • Ordering Code EPM2210F324I5N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210GF256I5N

  • MM# 974597
  • Spec Code SRBZR
  • Ordering Code EPM2210GF256I5N
  • Stepping A1

MAX® II EPM2210 CPLD EPM2210GF324C4

  • MM# 974599
  • Spec Code SRBZT
  • Ordering Code EPM2210GF324C4
  • Stepping A1

Trade compliance information

  • ECCN 3A991
  • CCATS NA
  • US HTS 8542390001

PCN/MDDS Information

SR9KG

SR6RN

SR8NG

SR6RL

SR9T8

SRBZT

SR9T6

SR9KL

SRBZR

SR9KK

SR9T4

SR9KJ

SR6AB

SRBAD

SRBAC

SR8ND

SR6RH

SR9TC

Drivers and Software

Latest Drivers & Software

Downloads Available:
All

Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Equivalent Macrocells

Typical equivalent macrocell" ratio is approximately 1.3 LEs per macrocell based on empirical data.

Pin-to-pin Delay

Pin-to-pin delay is the time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.

User Flash Memory

The User Flash Memory (UFM) provides access to the serial flash memory blocks in these devices.

Boundary-scan JTAG

Testing that isolates a device's internal circuitry from its I/O circuitry.

JTAG ISP

In-System Programmability via JTAG interface.

Fast Input Registers

Input registers in I/O cells that have a fast, direct connection from I/O pins.

Programmable Register Power-up

Enable registered outputs to drive high for a specific duration upon power-up through the Quartus II software.

JTAG Translator

Allow access to the JTAG TAP and state signals when either the USER0 or USER1 instruction is issued to the JTAG TAP.

Real-time ISP

Can program the supported device while the device is still in operation.

MultiVolt I/Os†

Allow devices in all packages to interface with systems of different supply voltages. An external resistor must be used for 5.0 V tolerance.

I/O Power Banks

A group of I/O pins that are grouped for the purpose of specifying I/O standards. To be powered up during device operation.

Maximum Output Enables

Maximum number of control inputs that either permit or prevent the output of data from the device.

LVTTL/LVCMOS

Low Voltage Transistor to Transistor Logic / Low Voltage Complementary Metal Oxide Semiconductor

32 bit, 66 MHz PCI Compliant

Note: this product requires an external resistor for 5V tolerance.

Schmitt Triggers

Allow input buffers to respond to slow input edge rates with a fast output edge rate.

Programmable Slew Rate

Output slew rate control that can be configured for low noise or high-speed performance.

Programmable Pull-up Resistors

Each I/O pin on the device provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor holds the output to the VCCIO level of the output pin’s bank.

Programmable GND Pins

Each unused I/O pin on the device can be used as an additional ground pin.

Open-drain Outputs

Devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals that can be asserted by any of several devices.

Bus Hold

Each I/O pin on the device provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.