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  • Brand Name: Core Ultra

  • Product Number: 6526Y

  • Ordering Code: PK8072205559500

  • SPEC Code: SRN6N

  • Code Name: Emerald Rapids

MAX® V 5M160Z CPLD

Specifications

Export specifications

Essentials

Package Specifications

  • Package Options M68, M100, E64, T100
  • Package Size 5mm x 5mm, 6mm x 6mm, 9mm x 9mm, 16mm x 16mm

Supplemental Information

Ordering and Compliance

Ordering and spec information

MAX® V 5M160Z CPLD 5M160ZM68C5N

  • MM# 965737
  • Spec Code SR4T4
  • Ordering Code 5M160ZM68C5N
  • Stepping A1
  • MDDS Content IDs 745168,  693144

MAX® V 5M160Z CPLD 5M160ZM68C4N

  • MM# 966142
  • Spec Code SR54Y
  • Ordering Code 5M160ZM68C4N
  • Stepping A1
  • MDDS Content IDs 745494,  694704

MAX® V 5M160Z CPLD 5M160ZM68I5N

  • MM# 966143
  • Spec Code SR54Z
  • Ordering Code 5M160ZM68I5N
  • Stepping A1
  • MDDS Content IDs 744494,  701525

MAX® V 5M160Z CPLD 5M160ZM100C5N

  • MM# 968400
  • Spec Code SR71C
  • Ordering Code 5M160ZM100C5N
  • Stepping A1
  • MDDS Content IDs 745666,  696363

MAX® V 5M160Z CPLD 5M160ZM100I5N

  • MM# 969129
  • Spec Code SR7NK
  • Ordering Code 5M160ZM100I5N
  • Stepping A1
  • MDDS Content IDs 745583,  694494

MAX® V 5M160Z CPLD 5M160ZM100C4N

  • MM# 970648
  • Spec Code SR8VV
  • Ordering Code 5M160ZM100C4N
  • Stepping A1
  • MDDS Content IDs 745946,  692256

Trade compliance information

  • ECCN EAR99
  • CCATS NA
  • US HTS 8542390001

PCN Information

SR4T4

SR7NK

SR54Z

SR54Y

SR71C

SR8VV

Drivers and Software

Latest Drivers & Software

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Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Equivalent Macrocells

Typical equivalent macrocell" ratio is approximately 1.3 LEs per macrocell based on empirical data.

Pin-to-pin Delay

Pin-to-pin delay is the time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin.

User Flash Memory

The User Flash Memory (UFM) provides access to the serial flash memory blocks in these devices.

Logic Convertible To Memory

Unused LEs can be converted to memory. The total number of available LE RAM bits depends on the memory mode, depth and width configurations of the instantiated memory.

Internal Oscillator

The internal oscillator is used to meet the clocking requirements of many designs and eliminate the requirement for an external clock circuitry.

Fast Power-on Reset

Fast reset of the entire design to an initial and well-known state after the power supply is detected.

Boundary-scan JTAG

Testing that isolates a device's internal circuitry from its I/O circuitry.

JTAG ISP

In-System Programmability via JTAG interface.

Fast Input Registers

Input registers in I/O cells that have a fast, direct connection from I/O pins.

Programmable Register Power-up

Enable registered outputs to drive high for a specific duration upon power-up through the Quartus II software.

JTAG Translator

Allow access to the JTAG TAP and state signals when either the USER0 or USER1 instruction is issued to the JTAG TAP.

Real-time ISP

Can program the supported device while the device is still in operation.

MultiVolt I/Os†

Allow devices in all packages to interface with systems of different supply voltages. †An external resistor must be used for 5.0 V tolerance.

I/O Power Banks

A group of I/O pins that are grouped for the purpose of specifying I/O standards. To be powered up during device operation.

Maximum Output Enables

Maximum number of control inputs that either permit or prevent the output of data from the device.

LVTTL/LVCMOS

Low Voltage Transistor to Transistor Logic / Low Voltage Complementary Metal Oxide Semiconductor

Emulated LVDS Outputs

Low Voltage Differential Signaling outputs

Schmitt Triggers

Allow input buffers to respond to slow input edge rates with a fast output edge rate.

Programmable Slew Rate

Output slew rate control that can be configured for low noise or high-speed performance.

Programmable Pull-up Resistors

Each I/O pin on the device provides an optional programmable pull-up resistor during user mode. If this feature is enabled for an I/O pin, the pull-up resistor holds the output to the VCCIO level of the output pin’s bank.

Programmable GND Pins

Each unused I/O pin on the device can be used as an additional ground pin.

Open-drain Outputs

Devices provide an optional open-drain (equivalent to open-collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals that can be asserted by any of several devices.

Bus Hold

Each I/O pin on the device provides an optional bus-hold feature. The bus-hold circuitry can hold the signal on an I/O pin at its last-driven state.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.

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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.

Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.

Refer to Datasheet for formal definitions of product properties and features.

‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.

“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.