Intel Agilex® 7 FPGA F-Series 027
Specifications
Compare Intel® Products
Essentials
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Product Collection
Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
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Marketing Status
Launched
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Launch Date
Q2'19
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Expected Discontinuance
1
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Lithography
10 nm
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Use Conditions
Base Transceiver Station
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Resources
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Logic Elements (LE)
2692760
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Adaptive Logic Modules (ALM)
912800
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Adaptive Logic Module (ALM) Registers
3651200
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Fabric and I/O Phase-Locked Loops (PLLs)
28
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Maximum Embedded Memory
287 Mb
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Maximum High Bandwidth Memory (HBM)†
1 GB
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Digital Signal Processing (DSP) Blocks
8528
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Digital Signal Processing (DSP) Format
Bfloat, Block Floating Point, Floating Point (hard IP), Multiply, Multiply and Accumulate, Variable Precision
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Hard Processor System (HPS)
Quad-core 64 bit Arm* Cortex*-A53
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Hard Crypto Blocks
1
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, QDR IV
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User-Flashable Memory
Yes
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Internal Configuration Storage
Yes
I/O Specifications
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Maximum User I/O Count†
624
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I/O Standards Support
1.2 V LVCMOS, 1.8 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, True Differential Signaling
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Maximum LVDS Pairs
312
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Maximum Non-Return to Zero (NRZ) Transceivers†
24
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Maximum Non-Return to Zero (NRZ) Data Rate†
28.9 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
12
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
57.8 Gbps
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Transceiver Protocol Hard IP
PCIe Gen4, 10/25/100G Ethernet
Advanced Technologies
Package Specifications
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Package Options
R2581A
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SRL5A
- 99ANK6 PCN
SRL5B
- 99ANK7 PCN
SRL5D
- 99ANK9 PCN
SRL5E
- 99ANKA PCN
SRL5F
- 99ANKC PCN
SRKGK
- 99A90D PCN
SRKGC
- 99A905 PCN
SRKGD
- 99A906 PCN
SRKGE
- 99A907 PCN
SRKGF
- 99A908 PCN
SRKGG
- 99A909 PCN
SRKGH
- 99A90A PCN
SRKGJ
- 99A90C PCN
SRL0G
- 99AKV0 PCN
SRL0H
- 99AKV1 PCN
SRKGA
- 99A903 PCN
SRKGB
- 99A904 PCN
SRKG4
- 99A8ZW PCN
SRKG5
- 99A8ZX PCN
SRKG6
- 99A8ZZ PCN
SRKG7
- 99A900 PCN
SRKG8
- 99A901 PCN
SRKG9
- 99A902 PCN
SRKZP
- 99AK4W PCN
SRKZQ
- 99AK4X PCN
SRL5M
- 99ANKK PCN
Drivers and Software
Description
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Expected Discontinuance
Expected Discontinuance is an estimate of when a product will begin the Product Discontinuance process. The Product Discontinuance Notification (PDN), published at the start of the discontinuance process, will include all EOL Key Milestone details. Some business units may communicate EOL timeline details before the PDN is published. Contact your Intel representative for information on EOL timelines and extended life options.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Use Conditions
Use conditions are the environmental and operating conditions derived from the context of system use.
For SKU specific use condition information, see PRQ report.
For current use condition information, see Intel UC (CNDA site)*.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Maximum High Bandwidth Memory (HBM)†
The total capacity of all the in-package high-bandwidth memory stacks in the Intel device or component.
† Actual count could be lower depending on package.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
User-Flashable Memory
User-flashable memory is a non-volatile memory resource available in some Intel FPGA device families.
Internal Configuration Storage
Intel FPGAs store configuration data either in internal configuration storage, or in external memory devices.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Analog-to-Digital Converter
The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.