Intel® PAC With Intel® Arria® 10 GX FPGA
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External Onboard DDR4
8 GB (4 GB x 2 banks)
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs, Intel® Quartus® Prime Software, Open Programmable Acceleration Engine (OPAE), Intel® Distribution of OpenVINO™ toolkit
Intel Programmable Acceleration Card w/ Intel Arria 10 GX FPGA is a high-performance workload acceleration solution for applications such as big data analytics, artificial intelligence, genomics, video transcoding, cybersecurity, and financial trading.
Intel® Server System R2000WFR Family
Intel® Server Board S2600WFR Family
Drivers and Software
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The date the product was first introduced.
Field programmable gate arrays (FPGAs) are integrated circuits that enable designers to program customized digital logic in the field.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Each FPGA mounted on a programmable acceleration card contains digital signal processor (DSP) blocks within the FPGA architecture. DSPs are used to filter and compress real-world analog signals. The dedicated DSP blocks within the FPGA have been optimized to implement various common DSP functions with maximum performance and minimum logic resource utilization.
PCI Express Revision
PCI Express Revision is the supported version of the PCI Express standard. Peripheral Component Interconnect Express (or PCIe) is a high-speed serial computer expansion bus standard for attaching hardware devices to a computer. The different PCI Express versions support different data rates.
PCI Express Configurations ‡
PCI Express (PCIe) Configurations describe the available PCIe lane configurations that can be used to link to PCIe devices.
Intel PACs are equipped with QSFP (eg QSFP+, QSFP28) cages on the front panel of the board. Please refer to product datasheet for a list of Intel-supported connectors. For volume deployment, customers are required to use Intel-validated QSFP modules.
Thermal Solution Specification
Intel Reference Heat Sink specification for proper operation of this processor.
Thermal Design Power (TDP) represents the average power, in watts, the processor dissipates when operating at Base Frequency with all cores active under an Intel-defined, high-complexity workload. Refer to Datasheet for thermal solution requirements.
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All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for informational purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.
System and Maximum TDP is based on worst case scenarios. Actual TDP may be lower if not all I/Os for chipsets are used.