Arria® V 5AGXB7 FPGA

Specifications

I/O Specifications

Package Specifications

Supplemental Information

Ordering and Compliance

Ordering and spec information

Arria® V 5AGXB7 FPGA 5AGXFB7H4F35I3G

  • MM# 973709
  • Spec Code SRBLA
  • Ordering Code 5AGXFB7H4F35I3G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 702456745254

Arria® V 5AGXB7 FPGA 5AGXFB7H4F35C5G

  • MM# 999FZP
  • Spec Code SRFKB
  • Ordering Code 5AGXFB7H4F35C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 697438

Arria® V 5AGXB7 FPGA 5AGXFB7H4F35I5G

  • MM# 999FZR
  • Spec Code SRFKC
  • Ordering Code 5AGXFB7H4F35I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 702599744507

Arria® V 5AGXB7 FPGA 5AGXFB7K4F40C5G

  • MM# 999FZT
  • Spec Code SRFKD
  • Ordering Code 5AGXFB7K4F40C5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 746654701903

Arria® V 5AGXB7 FPGA 5AGXBB7D4F35C4G

  • MM# 999X9K
  • Spec Code SRH9W
  • Ordering Code 5AGXBB7D4F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 700620

Arria® V 5AGXB7 FPGA 5AGXBB7D4F35C5G

  • MM# 999X9L
  • Spec Code SRH9X
  • Ordering Code 5AGXBB7D4F35C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 701591

Arria® V 5AGXB7 FPGA 5AGXBB7D4F35I5G

  • MM# 999X9M
  • Spec Code SRH9Y
  • Ordering Code 5AGXBB7D4F35I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 745233695579

Arria® V 5AGXB7 FPGA 5AGXBB7D4F40C4G

  • MM# 999X9N
  • Spec Code SRH9Z
  • Ordering Code 5AGXBB7D4F40C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 693255

Arria® V 5AGXB7 FPGA 5AGXBB7D4F40C5G

  • MM# 999X9P
  • Spec Code SRHA0
  • Ordering Code 5AGXBB7D4F40C5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 701330

Arria® V 5AGXB7 FPGA 5AGXBB7D4F40I5G

  • MM# 999X9R
  • Spec Code SRHA1
  • Ordering Code 5AGXBB7D4F40I5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 696643

Arria® V 5AGXB7 FPGA 5AGXBB7D6F35C6G

  • MM# 999X9T
  • Spec Code SRHA2
  • Ordering Code 5AGXBB7D6F35C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 700523

Arria® V 5AGXB7 FPGA 5AGXBB7D6F40C6G

  • MM# 999X9V
  • Spec Code SRHA3
  • Ordering Code 5AGXBB7D6F40C6G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 692122

Arria® V 5AGXB7 FPGA 5AGXFB7H4F35C4G

  • MM# 999XA6
  • Spec Code SRHAC
  • Ordering Code 5AGXFB7H4F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 702140

Arria® V 5AGXB7 FPGA 5AGXFB7H6F35C6G

  • MM# 999XA8
  • Spec Code SRHAD
  • Ordering Code 5AGXFB7H6F35C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 701566

Arria® V 5AGXB7 FPGA 5AGXFB7K4F40C4G

  • MM# 999XA9
  • Spec Code SRHAE
  • Ordering Code 5AGXFB7K4F40C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 744931700636

Arria® V 5AGXB7 FPGA 5AGXFB7K4F40I3G

  • MM# 999XAA
  • Spec Code SRHAF
  • Ordering Code 5AGXFB7K4F40I3G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 744926699332

Arria® V 5AGXB7 FPGA 5AGXFB7K4F40I5G

  • MM# 999XAC
  • Spec Code SRHAG
  • Ordering Code 5AGXFB7K4F40I5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 692513

Arria® V 5AGXB7 FPGA 5AGXFB7K6F40C6G

  • MM# 999XAD
  • Spec Code SRHAH
  • Ordering Code 5AGXFB7K6F40C6G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 702541

Arria® V 5AGXB7 FPGA 5AGXMB7G4F35C4G

  • MM# 999XAP
  • Spec Code SRHAR
  • Ordering Code 5AGXMB7G4F35C4G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 698185

Arria® V 5AGXB7 FPGA 5AGXMB7G4F35C5G

  • MM# 999XAR
  • Spec Code SRHAS
  • Ordering Code 5AGXMB7G4F35C5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 695027

Arria® V 5AGXB7 FPGA 5AGXMB7G4F35I5G

  • MM# 999XAT
  • Spec Code SRHAT
  • Ordering Code 5AGXMB7G4F35I5G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 745468698407

Arria® V 5AGXB7 FPGA 5AGXMB7G4F40C4G

  • MM# 999XAV
  • Spec Code SRHAU
  • Ordering Code 5AGXMB7G4F40C4G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 693327

Arria® V 5AGXB7 FPGA 5AGXMB7G4F40C5G

  • MM# 999XAW
  • Spec Code SRHAV
  • Ordering Code 5AGXMB7G4F40C5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 694874

Arria® V 5AGXB7 FPGA 5AGXMB7G4F40I5G

  • MM# 999XAX
  • Spec Code SRHAW
  • Ordering Code 5AGXMB7G4F40I5G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 693807

Arria® V 5AGXB7 FPGA 5AGXMB7G6F35C6G

  • MM# 999XH7
  • Spec Code SRHE4
  • Ordering Code 5AGXMB7G6F35C6G
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 700453

Arria® V 5AGXB7 FPGA 5AGXMB7G6F40C6G

  • MM# 999XH8
  • Spec Code SRHE5
  • Ordering Code 5AGXMB7G6F40C6G
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 696894

Retired and discontinued

Arria® V 5AGXB7 FPGA 5AGXMB7G4F35C4N

  • MM# 970572
  • Spec Code SR8TM
  • Ordering Code 5AGXMB7G4F35C4N
  • Stepping A1
  • ECCN 3A991
  • CCATS NA
  • MDDS Content IDs 744594696318

Arria® V 5AGXB7 FPGA 5AGXMB7G4F40C4N

  • MM# 970573
  • Spec Code SR8TN
  • Ordering Code 5AGXMB7G4F40C4N
  • Stepping A1
  • ECCN 3A001.A.7.A
  • CCATS G171972
  • MDDS Content IDs 693157

Trade compliance information

  • ECCN Varies By Product
  • CCATS Varies By Product
  • US HTS 8542390001

PCN Information

SR8TN

SR8TM

SRHAH

SRHAW

SRHAV

SRHAU

SRHAT

SRHAS

SRHAR

SRBLA

SRFKD

SRHAG

SRHAF

SRHAE

SRHAD

SRHAC

SRFKC

SRFKB

SRHA3

SRHA2

SRHA1

SRHE5

SRHA0

SRHE4

SRH9W

SRH9Z

SRH9Y

SRH9X

Drivers and Software

Latest Drivers & Software

Downloads Available:
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Name

Launch Date

The date the product was first introduced.

Lithography

Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.

Logic Elements (LE)

Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.

Adaptive Logic Modules (ALM)

The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.

Adaptive Logic Module (ALM) Registers

ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.

Fabric and I/O Phase-Locked Loops (PLLs)

Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.

Maximum Embedded Memory

The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.

Digital Signal Processing (DSP) Blocks

The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.

Digital Signal Processing (DSP) Format

Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.

Hard Memory Controllers

Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.

External Memory Interfaces (EMIF)

The external memory interface protocols supported by the Intel FPGA device.

Maximum User I/O Count

The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

I/O Standards Support

The general purpose I/O interface standards supported by the Intel FPGA device.

Maximum LVDS Pairs

The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.

Maximum Non-Return to Zero (NRZ) Transceivers

The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.

Maximum Non-Return to Zero (NRZ) Data Rate

The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.

Transceiver Protocol Hard IP

Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.

FPGA Bitstream Security

Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.

Analog-to-Digital Converter

The analog-to-digital converter is a data-converter resource available in some Intel FPGA device families.

Package Options

Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.