Intel Agilex® 7 FPGA F-Series 023
Specifications
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Essentials
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Product Collection
Intel Agilex® 7 FPGAs and SoC FPGAs F-Series
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Marketing Status
Launched
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Launch Date
Q2'21
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Lithography
10 nm
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Resources
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Logic Elements (LE)
2308080
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Adaptive Logic Modules (ALM)
782400
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Adaptive Logic Module (ALM) Registers
3129600
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Fabric and I/O Phase-Locked Loops (PLLs)
15
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Maximum Embedded Memory
246 Mb
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Digital Signal Processing (DSP) Blocks
1640
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Digital Signal Processing (DSP) Format
Fixed Point (hard IP), Floating Point (hard IP), Multiply, Multiply and Accumulate, Variable Precision
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Hard Processor System (HPS)
Quad-core 64 bit Arm* Cortex*-A53
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Hard Crypto Blocks
2
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Hard Memory Controllers
Yes
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External Memory Interfaces (EMIF)
DDR4, QDR IV
I/O Specifications
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Maximum User I/O Count†
480
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I/O Standards Support
1.2 V LVCMOS, 1.8 V LVCMOS, SSTL, POD, HSTL, HSUL, Differential SSTL, Differential POD, Differential HSTL, Differential HSUL, True Differential Signaling
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Maximum LVDS Pairs
240
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Maximum Non-Return to Zero (NRZ) Transceivers†
64
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Maximum Non-Return to Zero (NRZ) Data Rate†
32 Gbps
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Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
48
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Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
58 Gbps
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Transceiver Protocol Hard IP
PCIe Gen4, 10/25/50/100/200/400G Ethernet
Advanced Technologies
Package Specifications
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Package Options
R3184C
Supplemental Information
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Additional Information
Product Table (Family Comparison)
Datasheet
All FPGA Documentation
Ordering and Compliance
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Ordering and spec information
Intel Agilex® 7 FPGA F-Series 023 (R31C) AGFB023R31C2E1VB
- MM# 99CAPW
- Spec Code SRMW2
- Ordering Code AGFB023R31C2E1VB
- Stepping A2
- ECCN 5A002U
- CCATS G178951
Trade compliance information
- ECCN Varies By Product
- CCATS Varies By Product
- US HTS 8542390001
PCN Information
SRMTD
- 99CALK PCN
SRMT6
- 99CALA PCN
SRMT7
- 99CALC PCN
SRLR7
- 99AXCX PCN
SRLR8
- 99AXCZ PCN
SRLQX
- 99AXCJ PCN
SRLQY
- 99AXCK PCN
SRLR3
- 99AXCR PCN
SRLR4
- 99AXCT PCN
SRLQD
- 99AX9J PCN
SRLQF
- 99AX9Z PCN
SRLQG
- 99AXA8 PCN
SRLQH
- 99AXAD PCN
SRLQJ
- 99AXAT PCN
SRLQK
- 99AXAX PCN
SRLQC
- 99AX9H PCN
SRLQ6
- 99AX99 PCN
SRLPX
- 99AX90 PCN
SRLQ9
- 99AX9D PCN
SRLPZ
- 99AX92 PCN
SRLPK
- 99AX8J PCN
SRLTQ
- 99AXGZ PCN
SRLPN
- 99AX8M PCN
SRLTS
- 99AXH1 PCN
SRLU4
- 99AXHF PCN
SRLPP
- 99AX8N PCN
SRLTT
- 99AXH2 PCN
SRLPQ
- 99AX8P PCN
SRLQ2
- 99AX95 PCN
SRLTM
- 99AXGV PCN
SRLPJ
- 99AX8H PCN
SRLTE
- 99AXGK PCN
SRLPB
- 99AX88 PCN
SRLSV
- 99AXFX PCN
SRLP6
- 99AX83 PCN
SRLSY
- 99AXG1 PCN
SRLSN
- 99AXFM PCN
SRMQK
- 99C9TZ PCN
SRLT0
- 99AXG3 PCN
SRMQL
- 99C9V0 PCN
SRLSS
- 99AXFT PCN
SRLP2
- 99AX7Z PCN
SRLSG
- 99AXFF PCN
SRMQD
- 99C9T8 PCN
SRLSH
- 99AXFG PCN
SRMQE
- 99C9TA PCN
SRMQF
- 99C9TC PCN
SRMQG
- 99C9TL PCN
SRMQH
- 99C9TM PCN
SRLSL
- 99AXFK PCN
SRMQJ
- 99C9TW PCN
SRLSA
- 99AXF7 PCN
SRLSD
- 99AXFA PCN
SRLS7
- 99AXF4 PCN
SRLS9
- 99AXF6 PCN
SRLRY
- 99AXDT PCN
SRLRP
- 99AXDG PCN
SRLS2
- 99AXDZ PCN
SRLRS
- 99AXDK PCN
SRLS5
- 99AXF2 PCN
SRLRG
- 99AXD7 PCN
SRLVM
- 99AXKC PCN
SRLRL
- 99AXDC PCN
Drivers and Software
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Latest Drivers & Software
Launch Date
The date the product was first introduced.
Lithography
Lithography refers to the semiconductor technology used to manufacture an integrated circuit, and is reported in nanometer (nm), indicative of the size of features built on the semiconductor.
Logic Elements (LE)
Logic elements (LEs) are the smallest units of logic in Intel® FPGA architecture. LEs are compact and provide advanced features with efficient logic usage.
Adaptive Logic Modules (ALM)
The adaptive logic module (ALM) is the logic building block in supported Intel FPGA devices, and is designed to maximize both performance and utilization. Each ALM has several different modes of operation, and can implement a variety of different combinatorial and sequential logical functions.
Adaptive Logic Module (ALM) Registers
ALM registers are those register bits (flip-flops) that are contained inside the ALMs and are used to implement sequential logic.
Fabric and I/O Phase-Locked Loops (PLLs)
Fabric and IO PLLs are used to simplify the design and implementation of the clock networks in the Intel FPGA fabric, and also the clock networks associated with the IO cells in the device.
Maximum Embedded Memory
The total capacity of all the embedded memory blocks in the programmable fabric of the Intel FPGA device.
Digital Signal Processing (DSP) Blocks
The digital signal processing (DSP) block is the mathematical building block in supported Intel FPGA devices and contains high-performance multipliers and accumulators to implement a variety of digital signal processing functions.
Digital Signal Processing (DSP) Format
Depending on the Intel FPGA device family, the DSP block supports different formats such as hard floating point, hard fixed point, multiply and accumulate, and multiply only.
Hard Processor System (HPS)
The hard processor system (HPS) is a complete hard CPU system contained within the Intel FPGA fabric.
Hard Memory Controllers
Hard memory controllers are used to enable high-performance external memory systems attached to the Intel FPGA. A hard memory controller saves power and FPGA resources compared to the equivalent soft memory controller, and supports higher frequency operation.
External Memory Interfaces (EMIF)
The external memory interface protocols supported by the Intel FPGA device.
Maximum User I/O Count†
The maximum number of general purpose I/O pins in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
I/O Standards Support
The general purpose I/O interface standards supported by the Intel FPGA device.
Maximum LVDS Pairs
The maximum number of LVDS pairs that can be configured in the Intel FPGA device, in the largest available package. Refer to device documentation for actual RX and TX LVDS pairs count by package type.
Maximum Non-Return to Zero (NRZ) Transceivers†
The maximum number of NRZ transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Non-Return to Zero (NRZ) Data Rate†
The maximum NRZ data rate that is supported by the NRZ transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Maximum Pulse-Amplitude Modulation (PAM4) Transceivers†
The maximum number of PAM4 transceivers in the Intel FPGA device, in the largest available package.
† Actual count could be lower depending on package.
Maximum Pulse-Amplitude Modulation (PAM4) Data Rate†
The maximum PAM4 data rate that is supported by the PAM4 transceivers.
† Actual data rate could be lower depending on transceiver speed grade.
Transceiver Protocol Hard IP
Hard intellectual property available in the Intel FPGA device to support the high-speed serial transceivers. Transceiver protocol hard IP saves power and FPGA resources compared to the equivalent soft IP, and simplifies the implementation of the serial protocol.
Hyper-Registers
Hyper-Registers are additional register bits (flip-flops) located in the interconnect of some Intel FPGA device families, allowing for re-timing and pipelining of the interconnect to enable higher clock frequency in the FPGA fabric.
FPGA Bitstream Security
Depending on the Intel FPGA device family, various security features are available to prevent copying of the customer bitstream, and detect attempts to tamper with the device during operation.
Package Options
Intel FPGA devices are available in different package sizes, with different IO and transceiver counts, to match customer system requirements.
All information provided is subject to change at any time, without notice. Intel may make changes to manufacturing life cycle, specifications, and product descriptions at any time, without notice. The information herein is provided "as-is" and Intel does not make any representations or warranties whatsoever regarding accuracy of the information, nor on the product features, availability, functionality, or compatibility of the products listed. Please contact system vendor for more information on specific products or systems.
Intel classifications are for general, educational and planning purposes only and consist of Export Control Classification Numbers (ECCN) and Harmonized Tariff Schedule (HTS) numbers. Any use made of Intel classifications are without recourse to Intel and shall not be construed as a representation or warranty regarding the proper ECCN or HTS. Your company as an importer and/or exporter is responsible for determining the correct classification of your transaction.
Refer to Datasheet for formal definitions of product properties and features.
‡ This feature may not be available on all computing systems. Please check with the system vendor to determine if your system delivers this feature, or reference the system specifications (motherboard, processor, chipset, power supply, HDD, graphics controller, memory, BIOS, drivers, virtual machine monitor-VMM, platform software, and/or operating system) for feature compatibility. Functionality, performance, and other benefits of this feature may vary depending on system configuration.
“Announced” SKUs are not yet available. Please refer to the Launch Date for market availability.